In modern integrated circuits (ICs), high levels of functionality are achieved on a single chip by integrating large numbers of devices. One process commonly employed in achieving high circuit densities is by using back-end-of-line (BEOL) interconnect structures to link numerous devices, thereby forming a complex integrated circuit. BEOL interconnect structures are often fabricated by damascene processes, such as a dual damascene process in which a dielectric layer is deposited, vias and trenches are etched in the dielectric layer, and the vias and trenches are filled with a conductor using a single blanket deposition followed by planarization. This process is replicated to stack different conductive and via levels to create a multi-level, high density framework of conductive interconnections. As feature sizes continue to shrink with advances in technology, the dimensions of the interconnect structure spacing and thicknesses of the dielectric layers are correspondingly reduced. Reduced spacing between interconnect structures creates the potential for various issues, such as dielectric breakdown. It is therefore desirable to have improved BEOL interconnect structures and methods for fabricating BEOL interconnect structures to mitigate the aforementioned issues.